CoreEL WorkShop : Vivado Design Tool flow using Zed Board on May 25th, 2015

Dear ,

CoreEL University Program (CUP) team and Sandeepani invite you for a 1 days certified workshop as a awareness program on ZYNQ Architecture with VIVADO Design suite. 

Key Learnings:

After completing the course you will have the necessary understanding of Xilinx FPGA Architecture and skills to:

·         Introduction of VIVADO Design suite ·         Write RTL Verilog code for synthesis ·         Write Verilog test fixtures for simulation ·         Target and optimize Xilinx FPGAs by using Verilog Describe the supported design flows of the Vivado IDE ·         Create and manage designs within the Vivado™ Design Suite environment ·         Explore synthesis and implementation option and directives CoreEL Technologies  #607, 6th Floor, Welldone Tech Park, Sector-48, Sohna Road, Gurgaon - 122 001 Email: ankur.s@coreel.com Phone: 0124 424 5487

·         Take advantage of the primary features of the 7 series FPGAs ·         Use the PlanAhead™ tool to implement and simulate an FPGA design Generate the various reports at synthesis and implementation by using the Tcl Console or Flow Navigator to analyze the design Use the Schematic and Hierarchy viewers to analyze and cross probe the design Synthesize and implement the HDL design